Scaling Trends of Power Supply Noise in TSV-Based Three-Dimensional Integrated Circuits

Acknowledgments First, I would like to thank Professor Eby G. Friedman, my research and thesis adviser throughout my master's studies. It is his brilliant suggestion and patient guidance on my research that makes this work possible. His character of responsibility and wisdom on life deserves my study for my entire life. I appreciate the opportunity to work with Professor Eby G. Friedman and for all I've learned from him. I would like to thank Inna Vaisband from the High Performance VLSI/IC Design and Analysis Laboratory for her careful and patient instructions on editorial skills to help me with writing this thesis. for their willingness to share their knowledge of their respective fields of expertise. It has been a happy time working with them in the lab. Finally, I would like to thank my parents, Jianping Guo and Huisheng Xu, for all of their psychological and emotional support throughout the master's program for which I am forever grateful. Abstract The purpose of this thesis is to efficiently analyze power supply noise in three-dimensional integrated circuits (3-D ICs) when considering CMOS (Complementary metal–oxide–semiconductor) and through silicon via (TSV) technology scaling. The effects of different 3-D IC fabrication processes such as different 3-D manufacture methods and TSV technologies on power noise is discussed in this thesis. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated in Cadence Spectre. Constant TSV aspect ratio and constant TSV area overhead scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of the power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. It is demonstrated that larger TSV aspect ratios and areas are more effective methods than TSV length scaling to lower inductive power noise in 3-D ICs. When the TSV technology becomes the primary performance or cost bottleneck for high performance 3-D ICs, increasing TSV area should be adopted to produce lower power noise. Tradeoffs among the TSV area, TSV technology, and power supply noise in 3-D ICs should therefore be carefully considered during the design of a 3-D power network. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise considering CMOS technology scaling. Expressions (1.1) – (1.9): the closed-form expressions characterizing the 3-D via resistance, inductance, and capacitance used throughout the thesis were developed by Table 1.1 Characteristics of two different CMOS scaling methods 16 Table …